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Home > TERATEC FORUM > Workshops
Workshops - Wednesday June 12
Workshop 5 - 14:00 to 17:30
Machine learning & Maintenance prédictive
Chaired by Erick JONQUIERE, AFNet et Jean-Laurent PHILIPPE, Intel
Real-Time Anomaly Detection Using Deep Learning to Predict Robot Failures
Intel is one of the largest semiconductor manufacturers in the world. Intel’s high-volume manufacturing sites employ a large number of robots to transport wafers within the plant. Robots faults affect production yield, equipment downtime and factory throughput. This presentation will explain how Intel uses AI to predict robot failures. The first part will review the algorithmic challenges: how to get data, how to analyze it, how to get “tagged” data, how to create a scalable solution, and how to create a good predictor. The second part will expose the engineering challenges: data size and frequency, IP sensitivity and security, latency and actuation, scale. And the final section will present what the actual solution looks like.
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Biography : Dr. Jean-Laurent Philippe is a Senior HPC Technical Specialist at Intel in the Data Center Group Sales. He works closely with large HPC/AI end user customers and with leading OEMs and HPC ecosystem partners to define and build the HPC/AI solutions meeting the growing demand for application performance and power efficiency. These solutions include not only the processing elements (microprocessors like the Intel® Xeon® processor families) but also the interconnect (Intel Omni-Path Architecture and Intel networking solutions), the storage (Intel SSD portfolio), and the Intel Tools (compilers, Intel Parallel Studio XE, …).
Dr. Philippe has been with Intel 25 years and has been in various positions in technical support and technical sales, and he has managed several teams and groups in technical presales. His previous position was Technical Director for Internet of Things at Intel EMEA, and his team’s charter was to enable and develop the ecosystem with end-to-end solutions for Internet of Things based on Intel building blocks for solutions, platforms, technologies and products. Dr. Philippe holds a PhD from INPG (Grenoble, France) in computer science (automatic parallelization for distributed-memory supercomputers) and applied mathematics (cryptography). Jean-Laurent Philippe owns 2 patents in Japan on automated parallelization techniques. |
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For any other information regarding the workshops, please contact :
Jean-Pascal JEGU
Tel : +33 (0)9 70 65 02 10
jean-pascal.jegu@teratec.fr
Campus TERATEC
2, rue de la Piquetterie
91680 BRUYERES-LE-CHATEL
France