Home > TERATEC FORUM > Workshop 4

TERATEC 2016 Forum
Workshop 4 - Wednesday, June 29 from 9:00 to 12:30
Specialised computing architectures : helpers or challengers ?

Power dissipation in integrated circuits and adiabatic solutions
Hervé FANET, ingénieur de recherche, CEA LETI

Abstract : This talk presents a detailed analysis of power dissipation in integrated circuits and compares CMOS technology with the disruptive NEMS (Nano Electrical Mechanical Systems) technology. The adiabatic principle of optimal charging of capacitors is introduced in order to understand the possible gain for reducing the active power. .

Bio : Hervé Fanet received in 1971 the engineer’s diploma from the “Ecole Supérieure d’Electrricité”. He was involved in detectors and electronic developments for high energy particle Physics. He joined CEA-LETI in 1996 and was in charge of medical imaging research and manager of integrated circuits design department. His current research topics include smart sensors and ultra-low power electronics. He has published 40 papers in journals and is author or co-author of five books.

Register now and get your badge here

  • TERATEC Forum is strictly reserved for professionals.
  • Participation to exhibition, conferences and workshops is free (subject to seats available)
  • On line registration is obligatory to attend exhibition, conferences or the workshops.
  • The Vigipirate security plan being raised to its highest level, it is mandatory to register online in advance and come with an identity card order to participate in TERATEC Forum.
  • The badge is free of charge and give you access to all events TERATEC Forum.

For any other information regarding the workshops, please contact :

Jean-Pascal JEGU
Tel : +33 (0)9 70 65 02 10
2, rue de la Piquetterie


© Ter@tec - All rights reserved - Lawful mention